Rambus on Track for 1TB/s Memory System Bandwidth

Rambus Inc’s Technical introduced progress in the company’s “Terabyte Bandwidth Initiative”  at a speech in Tokyo Dec 8, 2008.

The Terabyte Bandwidth Initiative is an effort to realize a bandwidth of 1 Tbyte/second between a single SoC and multiple DRAM components.

Rambus will use technologies from this effort in its “XDR 2″ next-generation DRAM specifications.

Memory systems are in need of further expansion in bandwidth and reduction in power consumption more than ever is the logic/need.

Terabyte Bandwidth Initiative developed a technology called “Fully Differential Memory Architecture (FDMA).”

Confusion starts here -

“FDMA uses “32X Data Rate,” a technology that enables data transmission of 16Gbps with a pair of differential signaling lines when the clock frequency is 500MHz. Through a technology called “FlexLink C/A,” which uses 32X Data Rate in C/A lines, the bandwidth is further expanded by reducing the number of C/A lines and increasing the number of data lines.”

Such approach becomes significant under the current circumstances, where the number of pins to address DRAM devices on the SoC side is limited.”

Rambus is planning to commercialize in or after 2010. With XDR 2, the company will realize a bandwidth of 51.2 Gbytes/second per DRAM chip using 32 data lines and a “16X Data Rate,” which allows a data transmission speed of 12.8Gbps with a pair of differential signaling lines when the clock frequency is 800MHz.”

Rambus says it can realize a Tbyte/second class bandwidth by lining up 16 units of these chips.”

—confusion ends, um, maybe —

Um, huh?

Reads to me like there’s going to be the capability to store a whole lot more of stuff that we’ll never be able to go back and find/read.